/*
 * Copyright (c) [2020], MediaTek Inc. All rights reserved.
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. and/or its licensors.
 * Except as otherwise provided in the applicable licensing terms with
 * MediaTek Inc. and/or its licensors, any reproduction, modification, use or
 * disclosure of MediaTek Software, and information contained herein, in whole
 * or in part, shall be strictly prohibited.
*/
//[File]            : bn1_wf_dma_top.h
//[Revision time]   : Tue Apr 30 15:35:20 2019
//[Description]     : This file is auto generated by CODA
//[Copyright]       : Copyright (C) 2019 Mediatek Incorportion. All rights reserved.

#ifndef __BN1_WF_DMA_TOP_REGS_H__
#define __BN1_WF_DMA_TOP_REGS_H__

#include "hal_common.h"

#ifdef __cplusplus
extern "C" {
#endif


//****************************************************************************
//
//                     BN1_WF_DMA_TOP CR Definitions                     
//
//****************************************************************************

#define BN1_WF_DMA_TOP_BASE                                    0x820f7000

#define BN1_WF_DMA_TOP_DCR0_ADDR                               (BN1_WF_DMA_TOP_BASE + 0x00) // 7000
#define BN1_WF_DMA_TOP_DCR1_ADDR                               (BN1_WF_DMA_TOP_BASE + 0x04) // 7004
#define BN1_WF_DMA_TOP_FQCR0_ADDR                              (BN1_WF_DMA_TOP_BASE + 0x10) // 7010
#define BN1_WF_DMA_TOP_FQCR1_ADDR                              (BN1_WF_DMA_TOP_BASE + 0x14) // 7014
#define BN1_WF_DMA_TOP_FQCR2_ADDR                              (BN1_WF_DMA_TOP_BASE + 0x18) // 7018
#define BN1_WF_DMA_TOP_BN0RXCFR0_ADDR                          (BN1_WF_DMA_TOP_BASE + 0x70) // 7070
#define BN1_WF_DMA_TOP_BN0RECFR0_ADDR                          (BN1_WF_DMA_TOP_BASE + 0x74) // 7074
#define BN1_WF_DMA_TOP_BN0RECFR1_ADDR                          (BN1_WF_DMA_TOP_BASE + 0x78) // 7078
#define BN1_WF_DMA_TOP_BN0VCFR0_ADDR                           (BN1_WF_DMA_TOP_BASE + 0x7C) // 707C
#define BN1_WF_DMA_TOP_BN0TCFR0_ADDR                           (BN1_WF_DMA_TOP_BASE + 0x80) // 7080
#define BN1_WF_DMA_TOP_BN0TCFR1_ADDR                           (BN1_WF_DMA_TOP_BASE + 0x84) // 7084
#define BN1_WF_DMA_TOP_BN0TMCFR0_ADDR                          (BN1_WF_DMA_TOP_BASE + 0x88) // 7088
#define BN1_WF_DMA_TOP_BN0TCFR2_ADDR                           (BN1_WF_DMA_TOP_BASE + 0x8C) // 708C
#define BN1_WF_DMA_TOP_DBG_BN0REC0_ADDR                        (BN1_WF_DMA_TOP_BASE + 0x90) // 7090
#define BN1_WF_DMA_TOP_DBG_BN0REC1_ADDR                        (BN1_WF_DMA_TOP_BASE + 0x94) // 7094
#define BN1_WF_DMA_TOP_DBG_BN0REC2_ADDR                        (BN1_WF_DMA_TOP_BASE + 0x98) // 7098
#define BN1_WF_DMA_TOP_DBG_BN0REC3_ADDR                        (BN1_WF_DMA_TOP_BASE + 0x9C) // 709C
#define BN1_WF_DMA_TOP_DBG_BN0REC4_ADDR                        (BN1_WF_DMA_TOP_BASE + 0xA0) // 70A0
#define BN1_WF_DMA_TOP_DBG_00_ADDR                             (BN1_WF_DMA_TOP_BASE + 0xD0) // 70D0
#define BN1_WF_DMA_TOP_DBG_01_ADDR                             (BN1_WF_DMA_TOP_BASE + 0xD4) // 70D4
#define BN1_WF_DMA_TOP_DBG_CTRL_ADDR                           (BN1_WF_DMA_TOP_BASE + 0xDC) // 70DC
#define BN1_WF_DMA_TOP_WTMR0_ADDR                              (BN1_WF_DMA_TOP_BASE + 0xE0) // 70E0
#define BN1_WF_DMA_TOP_WTMR1_ADDR                              (BN1_WF_DMA_TOP_BASE + 0xE4) // 70E4
#define BN1_WF_DMA_TOP_SPCR0_ADDR                              (BN1_WF_DMA_TOP_BASE + 0xEC) // 70EC
#define BN1_WF_DMA_TOP_BN0ICSCFR0_ADDR                         (BN1_WF_DMA_TOP_BASE + 0xF0) // 70F0
#define BN1_WF_DMA_TOP_BN0ICSCFR1_ADDR                         (BN1_WF_DMA_TOP_BASE + 0xF4) // 70F4
#define BN1_WF_DMA_TOP_DBG_RXS_01_ADDR                         (BN1_WF_DMA_TOP_BASE + 0x100) // 7100
#define BN1_WF_DMA_TOP_DBG_RXS_02_ADDR                         (BN1_WF_DMA_TOP_BASE + 0x104) // 7104
#define BN1_WF_DMA_TOP_DBG_RXS_03_ADDR                         (BN1_WF_DMA_TOP_BASE + 0x108) // 7108
#define BN1_WF_DMA_TOP_DBG_RXS_04_ADDR                         (BN1_WF_DMA_TOP_BASE + 0x10C) // 710C
#define BN1_WF_DMA_TOP_DBG_RXS_05_ADDR                         (BN1_WF_DMA_TOP_BASE + 0x110) // 7110
#define BN1_WF_DMA_TOP_DBG_RXS_06_ADDR                         (BN1_WF_DMA_TOP_BASE + 0x114) // 7114
#define BN1_WF_DMA_TOP_DBG_FID_01_ADDR                         (BN1_WF_DMA_TOP_BASE + 0x140) // 7140
#define BN1_WF_DMA_TOP_DBG_FID_02_ADDR                         (BN1_WF_DMA_TOP_BASE + 0x144) // 7144
#define BN1_WF_DMA_TOP_DBG_FID_03_ADDR                         (BN1_WF_DMA_TOP_BASE + 0x148) // 7148
#define BN1_WF_DMA_TOP_DBG_FID_04_ADDR                         (BN1_WF_DMA_TOP_BASE + 0x14C) // 714C




/* =====================================================================================

  ---DCR0 (0x820f7000 + 0x00)---

    RESERVED0[2..0]              - (RO) Reserved bits
    MAX_RX_PKT_LENGTH[15..3]     - (RW) Maximum available RX package length
                                     Unit: DDW
                                     If the RX package length is longer than this maximum value, the package header and payload will be dropped and only the RX status (RFB) will be written to SYSRAM.
                                     Note: This length excludes RFB length.
    VEC_DROP_EN[16]              - (RW) Enables RX vector drop function
                                     0: Disable RX vector drop function
                                     1: Enable RX vector drop function
                                     If an RX vector is sent to DMA and the current descriptor is SW owned, drop the RX vector and set a flag to MIB counter.
    TB_WB_DIS[17]                - (RW) disable HE TB PPDU response tx count and remaining tx count write back
                                     1'b0: enable write back
                                     1'h1: disable write back
    RXPKT_LOSS_W_VEC_EN[18]      - (RW) Enable vector packet without check RX data packet is valid or not
                                     0: Disable vector packet when RX data packet is not valid
                                     1: Enable to send vector packet as long as RX vector has been received
    MD_DIRECT_EN[19]             - (RW) Enables packet direct path from or to MD.
                                     0: Disable, TXS.DW0[20] = TXOP Limit Error
                                     1: Enable, TXS.DW0[20] = MD
    RXD_GROUP_EN[23..20]         - (RW) Enables RX status group for MCU
                                     Bit[0]: GROUP1
                                     Bit[1]: GROUP2
                                     Bit[2]: GROUP3
                                     Bit[3]: GROUP5
                                     1'h0: Disappear
                                     1'h1: Present
    PSE_INV_FID_DIS[25..24]      - (RW) Replace PSE_FID when it was 0xFFF(invalid FID) in TX, to avoid error indicator
                                     2'b00: disable, use original PSE_FID (even it was 0xFFF)
                                     2'b01: replace INVALID FID when case is NDP
                                     2'b10: replace INVALID FID when case are NDP or TX abort
                                     2'b11: replace all of the INVALID FID
    RXD_G3_RCPI_DIS[26]          - (RW) Disable RXD Group3 MSB for RCPI
                                     0: Enable, RXD.Group3 [63:32] = PVEC1 MSB
                                     1: Disable, RXD.Group3 [63:32] = RCPI
    DCR0_RSV1[31..27]            - (RW)  xxx 

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DCR0_DCR0_RSV1_ADDR                     BN1_WF_DMA_TOP_DCR0_ADDR
#define BN1_WF_DMA_TOP_DCR0_DCR0_RSV1_MASK                     0xF8000000                // DCR0_RSV1[31..27]
#define BN1_WF_DMA_TOP_DCR0_DCR0_RSV1_SHFT                     27
#define BN1_WF_DMA_TOP_DCR0_RXD_G3_RCPI_DIS_ADDR               BN1_WF_DMA_TOP_DCR0_ADDR
#define BN1_WF_DMA_TOP_DCR0_RXD_G3_RCPI_DIS_MASK               0x04000000                // RXD_G3_RCPI_DIS[26]
#define BN1_WF_DMA_TOP_DCR0_RXD_G3_RCPI_DIS_SHFT               26
#define BN1_WF_DMA_TOP_DCR0_PSE_INV_FID_DIS_ADDR               BN1_WF_DMA_TOP_DCR0_ADDR
#define BN1_WF_DMA_TOP_DCR0_PSE_INV_FID_DIS_MASK               0x03000000                // PSE_INV_FID_DIS[25..24]
#define BN1_WF_DMA_TOP_DCR0_PSE_INV_FID_DIS_SHFT               24
#define BN1_WF_DMA_TOP_DCR0_RXD_GROUP_EN_ADDR                  BN1_WF_DMA_TOP_DCR0_ADDR
#define BN1_WF_DMA_TOP_DCR0_RXD_GROUP_EN_MASK                  0x00F00000                // RXD_GROUP_EN[23..20]
#define BN1_WF_DMA_TOP_DCR0_RXD_GROUP_EN_SHFT                  20
#define BN1_WF_DMA_TOP_DCR0_MD_DIRECT_EN_ADDR                  BN1_WF_DMA_TOP_DCR0_ADDR
#define BN1_WF_DMA_TOP_DCR0_MD_DIRECT_EN_MASK                  0x00080000                // MD_DIRECT_EN[19]
#define BN1_WF_DMA_TOP_DCR0_MD_DIRECT_EN_SHFT                  19
#define BN1_WF_DMA_TOP_DCR0_RXPKT_LOSS_W_VEC_EN_ADDR           BN1_WF_DMA_TOP_DCR0_ADDR
#define BN1_WF_DMA_TOP_DCR0_RXPKT_LOSS_W_VEC_EN_MASK           0x00040000                // RXPKT_LOSS_W_VEC_EN[18]
#define BN1_WF_DMA_TOP_DCR0_RXPKT_LOSS_W_VEC_EN_SHFT           18
#define BN1_WF_DMA_TOP_DCR0_TB_WB_DIS_ADDR                     BN1_WF_DMA_TOP_DCR0_ADDR
#define BN1_WF_DMA_TOP_DCR0_TB_WB_DIS_MASK                     0x00020000                // TB_WB_DIS[17]
#define BN1_WF_DMA_TOP_DCR0_TB_WB_DIS_SHFT                     17
#define BN1_WF_DMA_TOP_DCR0_VEC_DROP_EN_ADDR                   BN1_WF_DMA_TOP_DCR0_ADDR
#define BN1_WF_DMA_TOP_DCR0_VEC_DROP_EN_MASK                   0x00010000                // VEC_DROP_EN[16]
#define BN1_WF_DMA_TOP_DCR0_VEC_DROP_EN_SHFT                   16
#define BN1_WF_DMA_TOP_DCR0_MAX_RX_PKT_LENGTH_ADDR             BN1_WF_DMA_TOP_DCR0_ADDR
#define BN1_WF_DMA_TOP_DCR0_MAX_RX_PKT_LENGTH_MASK             0x0000FFF8                // MAX_RX_PKT_LENGTH[15..3]
#define BN1_WF_DMA_TOP_DCR0_MAX_RX_PKT_LENGTH_SHFT             3

/* =====================================================================================

  ---DCR1 (0x820f7000 + 0x04)---

    DCR1_RSV3[11..0]             - (RW)  xxx 
    ABNOR_RX_STOP_EN[14..12]     - (RW) enable abnormal RX packet stop funciton
                                     1'b0: Keep from receiving & processing abnormal RX packet
                                     1'b1: drop the abnormal RX packet and reset RX path
    DCR1_RSV2[15]                - (RW)  xxx 
    DCR1_RSV1[30..16]            - (RW)  xxx 
    PSE_DIF_WRDY_EN[31]          - (RW) RX/VEC DMAs WIFI-PSE interface option
                                     Selects RX and VEC DMAs WF_PSE interface write-data ready control scheme.
                                     1'b0: Disable write-data ready control
                                     1'b1: Enable write-data ready control
                                     (Used for RX/VEC DMA only)

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DCR1_PSE_DIF_WRDY_EN_ADDR               BN1_WF_DMA_TOP_DCR1_ADDR
#define BN1_WF_DMA_TOP_DCR1_PSE_DIF_WRDY_EN_MASK               0x80000000                // PSE_DIF_WRDY_EN[31]
#define BN1_WF_DMA_TOP_DCR1_PSE_DIF_WRDY_EN_SHFT               31
#define BN1_WF_DMA_TOP_DCR1_DCR1_RSV1_ADDR                     BN1_WF_DMA_TOP_DCR1_ADDR
#define BN1_WF_DMA_TOP_DCR1_DCR1_RSV1_MASK                     0x7FFF0000                // DCR1_RSV1[30..16]
#define BN1_WF_DMA_TOP_DCR1_DCR1_RSV1_SHFT                     16
#define BN1_WF_DMA_TOP_DCR1_DCR1_RSV2_ADDR                     BN1_WF_DMA_TOP_DCR1_ADDR
#define BN1_WF_DMA_TOP_DCR1_DCR1_RSV2_MASK                     0x00008000                // DCR1_RSV2[15]
#define BN1_WF_DMA_TOP_DCR1_DCR1_RSV2_SHFT                     15
#define BN1_WF_DMA_TOP_DCR1_ABNOR_RX_STOP_EN_ADDR              BN1_WF_DMA_TOP_DCR1_ADDR
#define BN1_WF_DMA_TOP_DCR1_ABNOR_RX_STOP_EN_MASK              0x00007000                // ABNOR_RX_STOP_EN[14..12]
#define BN1_WF_DMA_TOP_DCR1_ABNOR_RX_STOP_EN_SHFT              12
#define BN1_WF_DMA_TOP_DCR1_DCR1_RSV3_ADDR                     BN1_WF_DMA_TOP_DCR1_ADDR
#define BN1_WF_DMA_TOP_DCR1_DCR1_RSV3_MASK                     0x00000FFF                // DCR1_RSV3[11..0]
#define BN1_WF_DMA_TOP_DCR1_DCR1_RSV3_SHFT                     0

/* =====================================================================================

  ---FQCR0 (0x820f7000 + 0x10)---

    FQ_TARG_WIDX[9..0]           - (RW) Target WLAN index
                                     Note: Do not change the value when FQ_EN is HIGH.
    RESERVED10[15..10]           - (RO) Reserved bits
    FQ_TARG_OM[21..16]           - (RW) Target OwnMAC/BSSID index
                                     Note: Do not change the value when FQ_EN is HIGH.
    RESERVED22[23..22]           - (RO) Reserved bits
    FQ_TARG_QID[30..24]          - (RW) Target queue index (LMAC port)
                                     Note: Do not change the value when FQ_EN is HIGH.
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_FQCR0_FQ_TARG_QID_ADDR                  BN1_WF_DMA_TOP_FQCR0_ADDR
#define BN1_WF_DMA_TOP_FQCR0_FQ_TARG_QID_MASK                  0x7F000000                // FQ_TARG_QID[30..24]
#define BN1_WF_DMA_TOP_FQCR0_FQ_TARG_QID_SHFT                  24
#define BN1_WF_DMA_TOP_FQCR0_FQ_TARG_OM_ADDR                   BN1_WF_DMA_TOP_FQCR0_ADDR
#define BN1_WF_DMA_TOP_FQCR0_FQ_TARG_OM_MASK                   0x003F0000                // FQ_TARG_OM[21..16]
#define BN1_WF_DMA_TOP_FQCR0_FQ_TARG_OM_SHFT                   16
#define BN1_WF_DMA_TOP_FQCR0_FQ_TARG_WIDX_ADDR                 BN1_WF_DMA_TOP_FQCR0_ADDR
#define BN1_WF_DMA_TOP_FQCR0_FQ_TARG_WIDX_MASK                 0x000003FF                // FQ_TARG_WIDX[9..0]
#define BN1_WF_DMA_TOP_FQCR0_FQ_TARG_WIDX_SHFT                 0

/* =====================================================================================

  ---FQCR1 (0x820f7000 + 0x14)---

    FQ_FID_CNT[11..0]            - (RO) Filter out FID count
                                     The maximum number is 4095.
                                     Note: This field is is valid only when FQ_STS is 1.
    RESERVED12[12]               - (RO) Reserved bits
    FQ_MODE[13]                  - (RW) Filter queue mode
                                     0: Filter queue with WIDX
                                     1: Filter queue with OMIDX
    FQ_STS[14]                   - (RO) FQ task's status
                                     0: FilterQueue status is invalid.
                                     1: FilterQueue status is valid.
    FQ_EN[15]                    - (RW) Enables "filter queue" task
                                     Write can enable the task.
                                     Write:
                                     0: Meaningless
                                     1: Enable filter queue task
                                     Note: This bit will be cleared by hardware when task is completed.
    FQ_DEST_PID[17..16]          - (RW) Destination port index
                                     2'b00: HIF
                                     2'b01: MCU
                                     2'b10: LMAC
                                     2'b11: PSE
                                     Note: Do not change the value when FQ_EN is HIGH.
    RESERVED18[23..18]           - (RO) Reserved bits
    FQ_DEST_QID[30..24]          - (RW) Destination queue index
                                     Note: Do not change the value when FQ_EN is HIGH.
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_FQCR1_FQ_DEST_QID_ADDR                  BN1_WF_DMA_TOP_FQCR1_ADDR
#define BN1_WF_DMA_TOP_FQCR1_FQ_DEST_QID_MASK                  0x7F000000                // FQ_DEST_QID[30..24]
#define BN1_WF_DMA_TOP_FQCR1_FQ_DEST_QID_SHFT                  24
#define BN1_WF_DMA_TOP_FQCR1_FQ_DEST_PID_ADDR                  BN1_WF_DMA_TOP_FQCR1_ADDR
#define BN1_WF_DMA_TOP_FQCR1_FQ_DEST_PID_MASK                  0x00030000                // FQ_DEST_PID[17..16]
#define BN1_WF_DMA_TOP_FQCR1_FQ_DEST_PID_SHFT                  16
#define BN1_WF_DMA_TOP_FQCR1_FQ_EN_ADDR                        BN1_WF_DMA_TOP_FQCR1_ADDR
#define BN1_WF_DMA_TOP_FQCR1_FQ_EN_MASK                        0x00008000                // FQ_EN[15]
#define BN1_WF_DMA_TOP_FQCR1_FQ_EN_SHFT                        15
#define BN1_WF_DMA_TOP_FQCR1_FQ_STS_ADDR                       BN1_WF_DMA_TOP_FQCR1_ADDR
#define BN1_WF_DMA_TOP_FQCR1_FQ_STS_MASK                       0x00004000                // FQ_STS[14]
#define BN1_WF_DMA_TOP_FQCR1_FQ_STS_SHFT                       14
#define BN1_WF_DMA_TOP_FQCR1_FQ_MODE_ADDR                      BN1_WF_DMA_TOP_FQCR1_ADDR
#define BN1_WF_DMA_TOP_FQCR1_FQ_MODE_MASK                      0x00002000                // FQ_MODE[13]
#define BN1_WF_DMA_TOP_FQCR1_FQ_MODE_SHFT                      13
#define BN1_WF_DMA_TOP_FQCR1_FQ_FID_CNT_ADDR                   BN1_WF_DMA_TOP_FQCR1_ADDR
#define BN1_WF_DMA_TOP_FQCR1_FQ_FID_CNT_MASK                   0x00000FFF                // FQ_FID_CNT[11..0]
#define BN1_WF_DMA_TOP_FQCR1_FQ_FID_CNT_SHFT                   0

/* =====================================================================================

  ---FQCR2 (0x820f7000 + 0x18)---

    FQ_HEAD_FID[11..0]           - (RO) First FID filtered by Filter-Queue task
                                     12'hFFF: Invalid value
                                     Others: Valid FID
                                     Note: This field is is valid only when FQ_STS is 1.
    RESERVED12[15..12]           - (RO) Reserved bits
    FQ_TAIL_FID[27..16]          - (RO) Last FID filltered by Filter-Queue task
                                     12'hFFF: Invalid value
                                     Others: Valid FID
                                     Note: This field is is valid only when FQ_STS is 1.
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_FQCR2_FQ_TAIL_FID_ADDR                  BN1_WF_DMA_TOP_FQCR2_ADDR
#define BN1_WF_DMA_TOP_FQCR2_FQ_TAIL_FID_MASK                  0x0FFF0000                // FQ_TAIL_FID[27..16]
#define BN1_WF_DMA_TOP_FQCR2_FQ_TAIL_FID_SHFT                  16
#define BN1_WF_DMA_TOP_FQCR2_FQ_HEAD_FID_ADDR                  BN1_WF_DMA_TOP_FQCR2_ADDR
#define BN1_WF_DMA_TOP_FQCR2_FQ_HEAD_FID_MASK                  0x00000FFF                // FQ_HEAD_FID[11..0]
#define BN1_WF_DMA_TOP_FQCR2_FQ_HEAD_FID_SHFT                  0

/* =====================================================================================

  ---BN0RXCFR0 (0x820f7000 + 0x70)---

    BN0_RX_QID[6..0]             - (RW) RX Data destination queue index
                                     default: send to queue4 (RX SEC)
                                     (For Debug)
    RESERVED7[7]                 - (RO) Reserved bits
    BN0_RX_PID[9..8]             - (RW) RX Data destination port index
                                     default: send to port2 (WLAN)
                                     (For Debug)
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_BN0RXCFR0_BN0_RX_PID_ADDR               BN1_WF_DMA_TOP_BN0RXCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0RXCFR0_BN0_RX_PID_MASK               0x00000300                // BN0_RX_PID[9..8]
#define BN1_WF_DMA_TOP_BN0RXCFR0_BN0_RX_PID_SHFT               8
#define BN1_WF_DMA_TOP_BN0RXCFR0_BN0_RX_QID_ADDR               BN1_WF_DMA_TOP_BN0RXCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0RXCFR0_BN0_RX_QID_MASK               0x0000007F                // BN0_RX_QID[6..0]
#define BN1_WF_DMA_TOP_BN0RXCFR0_BN0_RX_QID_SHFT               0

/* =====================================================================================

  ---BN0RECFR0 (0x820f7000 + 0x74)---

    BN0_RPT_QID[6..0]            - (RW) TXCMDRPT/TRIG-CMDRPT/RXRPT destination queue index (depends on port index)
                                     (For RPT)
    RESERVED7[7]                 - (RO) Reserved bits
    BN0_RPT_PID[9..8]            - (RW) TXCMDRPT/TRIG-CMDRPT/RXRPT destination port index
                                     2'h0: HIF
                                     2'h1: MCU
                                     (For RPT)
    RESERVED10[14..10]           - (RO) Reserved bits
    BN0_RXRPT_RXBUF_EN[15]       - (RW) RXRPT use PSE RX or CMDRPT page count for Buffer Allocation
                                     1'h0: use CMDRPT page count
                                     1'h1: use RXRPT page count
                                     (For RXRPT)
    BN0_RMACRPT_VEC_TOUT[25..16] - (RW) TRIG-CMDRPT/RXRPT with vector sequence timeout value
                                     0: disable
                                     Others: one RPT wait matching vector over tout*32us (max: 32.736ms)
                                     Unit: 32us
    BN0_AGGRPT_VEC_TOUT[31..26]  - (RW) TXCMDRPT with vector sequence timeout value
                                     0: disable
                                     Others: one RPT wait matching vector over tout*32us (max: 2.016ms)
                                     Unit: 32us

 =====================================================================================*/
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_AGGRPT_VEC_TOUT_ADDR      BN1_WF_DMA_TOP_BN0RECFR0_ADDR
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_AGGRPT_VEC_TOUT_MASK      0xFC000000                // BN0_AGGRPT_VEC_TOUT[31..26]
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_AGGRPT_VEC_TOUT_SHFT      26
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_RMACRPT_VEC_TOUT_ADDR     BN1_WF_DMA_TOP_BN0RECFR0_ADDR
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_RMACRPT_VEC_TOUT_MASK     0x03FF0000                // BN0_RMACRPT_VEC_TOUT[25..16]
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_RMACRPT_VEC_TOUT_SHFT     16
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_RXRPT_RXBUF_EN_ADDR       BN1_WF_DMA_TOP_BN0RECFR0_ADDR
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_RXRPT_RXBUF_EN_MASK       0x00008000                // BN0_RXRPT_RXBUF_EN[15]
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_RXRPT_RXBUF_EN_SHFT       15
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_RPT_PID_ADDR              BN1_WF_DMA_TOP_BN0RECFR0_ADDR
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_RPT_PID_MASK              0x00000300                // BN0_RPT_PID[9..8]
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_RPT_PID_SHFT              8
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_RPT_QID_ADDR              BN1_WF_DMA_TOP_BN0RECFR0_ADDR
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_RPT_QID_MASK              0x0000007F                // BN0_RPT_QID[6..0]
#define BN1_WF_DMA_TOP_BN0RECFR0_BN0_RPT_QID_SHFT              0

/* =====================================================================================

  ---BN0RECFR1 (0x820f7000 + 0x78)---

    BN0_RPTBUF_REMAIN_NUM[7..0]  - (RW) Report engine internal report buffer remaining number setting
                                     (For RPT)
    RESERVED8[15..8]             - (RO) Reserved bits
    BN0_VECBUF_REMAIN_NUM[23..16] - (RW) Report engine internal vector buffer remaining number setting
                                     (For VEC)
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_BN0RECFR1_BN0_VECBUF_REMAIN_NUM_ADDR    BN1_WF_DMA_TOP_BN0RECFR1_ADDR
#define BN1_WF_DMA_TOP_BN0RECFR1_BN0_VECBUF_REMAIN_NUM_MASK    0x00FF0000                // BN0_VECBUF_REMAIN_NUM[23..16]
#define BN1_WF_DMA_TOP_BN0RECFR1_BN0_VECBUF_REMAIN_NUM_SHFT    16
#define BN1_WF_DMA_TOP_BN0RECFR1_BN0_RPTBUF_REMAIN_NUM_ADDR    BN1_WF_DMA_TOP_BN0RECFR1_ADDR
#define BN1_WF_DMA_TOP_BN0RECFR1_BN0_RPTBUF_REMAIN_NUM_MASK    0x000000FF                // BN0_RPTBUF_REMAIN_NUM[7..0]
#define BN1_WF_DMA_TOP_BN0RECFR1_BN0_RPTBUF_REMAIN_NUM_SHFT    0

/* =====================================================================================

  ---BN0VCFR0 (0x820f7000 + 0x7C)---

    BN0_VEC2M[0]                 - (RW) Sets RX Vector to MCU
                                     1'b0: To HIF
                                     1'b1: To MCU
                                     (For RX)
    RESERVED1[7..1]              - (RO) Reserved bits
    BN0_VEC_AGG_CNT[10..8]       - (RW) RXV maximum aggregation count
                                     3'h00: 1 packet, no aggregation
                                     3'h01: Aggregate 1 packet
                                     3'h02: Aggregate 2 packets
                                     and so on
                                     The maximum aggregation count is 7.
                                     (For RX)
    BN0_VEC2H_QID[13..11]        - (RW) RXV HIF destination queue index
                                     3'h0: Queue index is 0 
                                     3'h1: Queue index is 1
                                     3'h2: Queue index is 2
                                     3'h3: Queue index is 3 
                                     3'h4: Queue index is 4
                                     3'h5: Queue index is 5
                                     3'h6~7: reserved
                                     (For RX)
    BN0_VEC2M_QID[15..14]        - (RW) RXV MCU destination queue index
                                     2'h0: Queue index is 0
                                     2'h1: Queue index is 1
                                     2'h2: Queue index is 2
                                     2'h3: Queue index is 3
                                     (For RX)
    BN0_VEC_TOUT[27..16]         - (RW) RXV timeout value
                                     Unit: 32us
                                     (For RX)
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC_TOUT_ADDR              BN1_WF_DMA_TOP_BN0VCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC_TOUT_MASK              0x0FFF0000                // BN0_VEC_TOUT[27..16]
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC_TOUT_SHFT              16
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC2M_QID_ADDR             BN1_WF_DMA_TOP_BN0VCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC2M_QID_MASK             0x0000C000                // BN0_VEC2M_QID[15..14]
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC2M_QID_SHFT             14
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC2H_QID_ADDR             BN1_WF_DMA_TOP_BN0VCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC2H_QID_MASK             0x00003800                // BN0_VEC2H_QID[13..11]
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC2H_QID_SHFT             11
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC_AGG_CNT_ADDR           BN1_WF_DMA_TOP_BN0VCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC_AGG_CNT_MASK           0x00000700                // BN0_VEC_AGG_CNT[10..8]
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC_AGG_CNT_SHFT           8
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC2M_ADDR                 BN1_WF_DMA_TOP_BN0VCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC2M_MASK                 0x00000001                // BN0_VEC2M[0]
#define BN1_WF_DMA_TOP_BN0VCFR0_BN0_VEC2M_SHFT                 0

/* =====================================================================================

  ---BN0TCFR0 (0x820f7000 + 0x80)---

    BN0_TXS2M_BITMAP[6..0]       - (RW) TXS-to-MCU classify bitmap
                                     0: Disable
                                     1: Enable
                                     If the related status bit {BAF,PS,TXOP,BE,LE,RE,ME} is 1, TXS will be forwarded to MCU.
                                     (For TX)
    RESERVED7[7]                 - (RO) Reserved bits
    BN0_TXS2M_AGG_CNT[12..8]     - (RW) TXS-to-MCU maximum aggregation count
                                     5'h00: 1 packet, no aggregation
                                     5'h01: Aggregate 1 packet
                                     5'h02: Aggregate 2 packets
                                     and so on
                                     The maximum aggregation count is 31.
                                     (For TX)
    BN0_TXS2M_QID[15..13]        - (RW) TXS MCU destination queue index
                                     2'h0: Qeue index is 0
                                     2'h1: Queue index is 1
                                     2'h2: Queue index is 2
                                     2'h3: Queue index is 3
                                     2'h4: Queue index is 4
                                     2'h5: Queue index is 5
                                     (For TX)
    BN0_TXS2M_TOUT[27..16]       - (RW) TXS-to-MCU timeout value
                                     Unit: 32us
                                     (For TX)
    RESERVED28[29..28]           - (RO) Reserved bits
    BN0_TXS2M_PID[31..30]        - (RW) TXS-to-MCU destination port index
                                     2'h0: HIF or WM-CPU (MAC_DMA0 or MAC_DMA1)
                                     2'h1: MCU
                                     (For TX)

 =====================================================================================*/
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_PID_ADDR             BN1_WF_DMA_TOP_BN0TCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_PID_MASK             0xC0000000                // BN0_TXS2M_PID[31..30]
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_PID_SHFT             30
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_TOUT_ADDR            BN1_WF_DMA_TOP_BN0TCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_TOUT_MASK            0x0FFF0000                // BN0_TXS2M_TOUT[27..16]
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_TOUT_SHFT            16
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_QID_ADDR             BN1_WF_DMA_TOP_BN0TCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_QID_MASK             0x0000E000                // BN0_TXS2M_QID[15..13]
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_QID_SHFT             13
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_AGG_CNT_ADDR         BN1_WF_DMA_TOP_BN0TCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_AGG_CNT_MASK         0x00001F00                // BN0_TXS2M_AGG_CNT[12..8]
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_AGG_CNT_SHFT         8
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_BITMAP_ADDR          BN1_WF_DMA_TOP_BN0TCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_BITMAP_MASK          0x0000007F                // BN0_TXS2M_BITMAP[6..0]
#define BN1_WF_DMA_TOP_BN0TCFR0_BN0_TXS2M_BITMAP_SHFT          0

/* =====================================================================================

  ---BN0TCFR1 (0x820f7000 + 0x84)---

    BN0_TXS2H_BITMAP[6..0]       - (RW) TXS-to-HIF classify bitmap
                                     0: Disable
                                     1: Enable
                                     If the related status bit {BAF,PS,TXOP,BE,LE,RE,ME} is 1, the TXS will be forwarded to HIF.
                                     (For TX)
    RESERVED7[7]                 - (RO) Reserved bits
    BN0_TXS2H_AGG_CNT[12..8]     - (RW) TXS-to-HIF maximum aggregation count
                                     5'h00: 1 packet, no aggregation
                                     5'h01: Aggregate 1 packet
                                     5'h02: Aggregate 2 packets
                                     and so on
                                     The maximum aggregation count is 31.
                                     (For TX)
    BN0_TXS2H_AP_QID[15..13]     - (RW) TXS HIF AP destination queue index
                                     3'h0: Queue index is 0
                                     3'h1: Queue index is 1 (default)
                                     3'h2: Queue index is 2
                                     3'h3: Queue index is 3
                                     etc,
                                     (For TX)
    BN0_TXS2H_TOUT[27..16]       - (RW) TXS-to-HIF timeout value
                                     Unit: 32us
                                     (For TX)
    RESERVED28[29..28]           - (RO) Reserved bits
    BN0_TXS2H_PID[31..30]        - (RW) TXS-to-HIF destination port index
                                     2'h0: HIF or WM-CPU (MAC_DMA0 or MAC_DMA1)
                                     2'h1: MCU
                                     (For TX)

 =====================================================================================*/
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_PID_ADDR             BN1_WF_DMA_TOP_BN0TCFR1_ADDR
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_PID_MASK             0xC0000000                // BN0_TXS2H_PID[31..30]
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_PID_SHFT             30
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_TOUT_ADDR            BN1_WF_DMA_TOP_BN0TCFR1_ADDR
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_TOUT_MASK            0x0FFF0000                // BN0_TXS2H_TOUT[27..16]
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_TOUT_SHFT            16
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_AP_QID_ADDR          BN1_WF_DMA_TOP_BN0TCFR1_ADDR
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_AP_QID_MASK          0x0000E000                // BN0_TXS2H_AP_QID[15..13]
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_AP_QID_SHFT          13
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_AGG_CNT_ADDR         BN1_WF_DMA_TOP_BN0TCFR1_ADDR
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_AGG_CNT_MASK         0x00001F00                // BN0_TXS2H_AGG_CNT[12..8]
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_AGG_CNT_SHFT         8
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_BITMAP_ADDR          BN1_WF_DMA_TOP_BN0TCFR1_ADDR
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_BITMAP_MASK          0x0000007F                // BN0_TXS2H_BITMAP[6..0]
#define BN1_WF_DMA_TOP_BN0TCFR1_BN0_TXS2H_BITMAP_SHFT          0

/* =====================================================================================

  ---BN0TMCFR0 (0x820f7000 + 0x88)---

    BN0_TMRI2M[0]                - (RW) Sets timing measurement report of initiator (TMR) packet to MCU
                                     1'b0: To HIF
                                     1'b1: To MCU
                                     (For TX/RX)
    BN0_TMRR2M[1]                - (RW) Set timing measurement report of responder (TMR) packet to MCU
                                     1'b0: To HIF
                                     1'b1: To MCU
                                     (For TX/RX)
    RESERVED2[10..2]             - (RO) Reserved bits
    BN0_TMR2H_QID[13..11]        - (RW) TMR HIF destination queue index
                                     3'h0: Queue index is 0
                                     3'h1: Queue index is 1
                                     3'h2: Queue index is 2
                                     3'h3: Queue index is 3
                                     3'h4: Queue index is 4
                                     3'h5: Queue index is 5
                                     3'h6~7: reserved
                                     (For TX/RX)
    BN0_TMR2M_QID[15..14]        - (RW) TMR MCU destination queue index
                                     2'h0: Queue index is 0
                                     2'h1: Queue index is 1
                                     2'h2: Queue index is 2
                                     2'h3: Queue index is 3
                                     (For TX/RX)
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_BN0TMCFR0_BN0_TMR2M_QID_ADDR            BN1_WF_DMA_TOP_BN0TMCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0TMCFR0_BN0_TMR2M_QID_MASK            0x0000C000                // BN0_TMR2M_QID[15..14]
#define BN1_WF_DMA_TOP_BN0TMCFR0_BN0_TMR2M_QID_SHFT            14
#define BN1_WF_DMA_TOP_BN0TMCFR0_BN0_TMR2H_QID_ADDR            BN1_WF_DMA_TOP_BN0TMCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0TMCFR0_BN0_TMR2H_QID_MASK            0x00003800                // BN0_TMR2H_QID[13..11]
#define BN1_WF_DMA_TOP_BN0TMCFR0_BN0_TMR2H_QID_SHFT            11
#define BN1_WF_DMA_TOP_BN0TMCFR0_BN0_TMRR2M_ADDR               BN1_WF_DMA_TOP_BN0TMCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0TMCFR0_BN0_TMRR2M_MASK               0x00000002                // BN0_TMRR2M[1]
#define BN1_WF_DMA_TOP_BN0TMCFR0_BN0_TMRR2M_SHFT               1
#define BN1_WF_DMA_TOP_BN0TMCFR0_BN0_TMRI2M_ADDR               BN1_WF_DMA_TOP_BN0TMCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0TMCFR0_BN0_TMRI2M_MASK               0x00000001                // BN0_TMRI2M[0]
#define BN1_WF_DMA_TOP_BN0TMCFR0_BN0_TMRI2M_SHFT               0

/* =====================================================================================

  ---BN0TCFR2 (0x820f7000 + 0x8C)---

    RESERVED0[11..0]             - (RO) Reserved bits
    BN0_TXS2H_MD_QID[15..12]     - (RW) TXS HIF MD destination queue index
                                     4'h0: Queue index is 0
                                     4'h1: Queue index is 1
                                     4'h2: Queue index is 2
                                     4'h3: Queue index is 3
                                     etc,
                                     4'hA: Queue index is 10 (default)
                                     (For TX)
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_BN0TCFR2_BN0_TXS2H_MD_QID_ADDR          BN1_WF_DMA_TOP_BN0TCFR2_ADDR
#define BN1_WF_DMA_TOP_BN0TCFR2_BN0_TXS2H_MD_QID_MASK          0x0000F000                // BN0_TXS2H_MD_QID[15..12]
#define BN1_WF_DMA_TOP_BN0TCFR2_BN0_TXS2H_MD_QID_SHFT          12

/* =====================================================================================

  ---DBG_BN0REC0 (0x820f7000 + 0x90)---

    BN0_RPT_RMAC_REQ_CNT[15..0]  - (RO) RMAC request Report Engine Count
                                     (For debug RPT)
    BN0_RPT_AGG_REQ_CNT[31..16]  - (RO) AGG request Report Engine Count
                                     (For debug RPT)

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_BN0REC0_BN0_RPT_AGG_REQ_CNT_ADDR    BN1_WF_DMA_TOP_DBG_BN0REC0_ADDR
#define BN1_WF_DMA_TOP_DBG_BN0REC0_BN0_RPT_AGG_REQ_CNT_MASK    0xFFFF0000                // BN0_RPT_AGG_REQ_CNT[31..16]
#define BN1_WF_DMA_TOP_DBG_BN0REC0_BN0_RPT_AGG_REQ_CNT_SHFT    16
#define BN1_WF_DMA_TOP_DBG_BN0REC0_BN0_RPT_RMAC_REQ_CNT_ADDR   BN1_WF_DMA_TOP_DBG_BN0REC0_ADDR
#define BN1_WF_DMA_TOP_DBG_BN0REC0_BN0_RPT_RMAC_REQ_CNT_MASK   0x0000FFFF                // BN0_RPT_RMAC_REQ_CNT[15..0]
#define BN1_WF_DMA_TOP_DBG_BN0REC0_BN0_RPT_RMAC_REQ_CNT_SHFT   0

/* =====================================================================================

  ---DBG_BN0REC1 (0x820f7000 + 0x94)---

    BN0_RPT_ENQ_TRIGCMDRPT_CNT[15..0] - (RO) DMA Enqueue Trigger-based CMDRPT Count
                                     (For debug RPT)
    BN0_RPT_ENQ_TXCMDRPT_CNT[31..16] - (RO) DMA Enqueue TXCMDRPT Count
                                     (For debug RPT)

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_BN0REC1_BN0_RPT_ENQ_TXCMDRPT_CNT_ADDR BN1_WF_DMA_TOP_DBG_BN0REC1_ADDR
#define BN1_WF_DMA_TOP_DBG_BN0REC1_BN0_RPT_ENQ_TXCMDRPT_CNT_MASK 0xFFFF0000                // BN0_RPT_ENQ_TXCMDRPT_CNT[31..16]
#define BN1_WF_DMA_TOP_DBG_BN0REC1_BN0_RPT_ENQ_TXCMDRPT_CNT_SHFT 16
#define BN1_WF_DMA_TOP_DBG_BN0REC1_BN0_RPT_ENQ_TRIGCMDRPT_CNT_ADDR BN1_WF_DMA_TOP_DBG_BN0REC1_ADDR
#define BN1_WF_DMA_TOP_DBG_BN0REC1_BN0_RPT_ENQ_TRIGCMDRPT_CNT_MASK 0x0000FFFF                // BN0_RPT_ENQ_TRIGCMDRPT_CNT[15..0]
#define BN1_WF_DMA_TOP_DBG_BN0REC1_BN0_RPT_ENQ_TRIGCMDRPT_CNT_SHFT 0

/* =====================================================================================

  ---DBG_BN0REC2 (0x820f7000 + 0x98)---

    BN0_RPT_ENQ_UNDEF_CNT[15..0] - (RO) DMA Enqueue undefined report type Count
                                     (For debug RPT)
    BN0_RPT_ENQ_RXRPT_CNT[31..16] - (RO) DMA Enqueue RXRPT Count
                                     (For debug RPT)

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_BN0REC2_BN0_RPT_ENQ_RXRPT_CNT_ADDR  BN1_WF_DMA_TOP_DBG_BN0REC2_ADDR
#define BN1_WF_DMA_TOP_DBG_BN0REC2_BN0_RPT_ENQ_RXRPT_CNT_MASK  0xFFFF0000                // BN0_RPT_ENQ_RXRPT_CNT[31..16]
#define BN1_WF_DMA_TOP_DBG_BN0REC2_BN0_RPT_ENQ_RXRPT_CNT_SHFT  16
#define BN1_WF_DMA_TOP_DBG_BN0REC2_BN0_RPT_ENQ_UNDEF_CNT_ADDR  BN1_WF_DMA_TOP_DBG_BN0REC2_ADDR
#define BN1_WF_DMA_TOP_DBG_BN0REC2_BN0_RPT_ENQ_UNDEF_CNT_MASK  0x0000FFFF                // BN0_RPT_ENQ_UNDEF_CNT[15..0]
#define BN1_WF_DMA_TOP_DBG_BN0REC2_BN0_RPT_ENQ_UNDEF_CNT_SHFT  0

/* =====================================================================================

  ---DBG_BN0REC3 (0x820f7000 + 0x9C)---

    BN0_RPT_CMDRPT_VEC_DROP_CNT[15..0] - (RO) CMDRPT VEC drop when CMDRPT page count is not enough count
                                     (For debug RPT)
    BN0_RPT_RXRPT_DROP_CNT[31..16] - (RO) RXRPT drop when CMDRPT page count is not enough count
                                     (For debug RPT)

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_BN0REC3_BN0_RPT_RXRPT_DROP_CNT_ADDR BN1_WF_DMA_TOP_DBG_BN0REC3_ADDR
#define BN1_WF_DMA_TOP_DBG_BN0REC3_BN0_RPT_RXRPT_DROP_CNT_MASK 0xFFFF0000                // BN0_RPT_RXRPT_DROP_CNT[31..16]
#define BN1_WF_DMA_TOP_DBG_BN0REC3_BN0_RPT_RXRPT_DROP_CNT_SHFT 16
#define BN1_WF_DMA_TOP_DBG_BN0REC3_BN0_RPT_CMDRPT_VEC_DROP_CNT_ADDR BN1_WF_DMA_TOP_DBG_BN0REC3_ADDR
#define BN1_WF_DMA_TOP_DBG_BN0REC3_BN0_RPT_CMDRPT_VEC_DROP_CNT_MASK 0x0000FFFF                // BN0_RPT_CMDRPT_VEC_DROP_CNT[15..0]
#define BN1_WF_DMA_TOP_DBG_BN0REC3_BN0_RPT_CMDRPT_VEC_DROP_CNT_SHFT 0

/* =====================================================================================

  ---DBG_BN0REC4 (0x820f7000 + 0xA0)---

    BN0_RMAC_VEC_DROP_CNT[7..0]  - (RO) TRIG-CMDRPT/RXRPT without matching vector count
                                     (For debug RPT)
    BN0_AGG_VEC_TOUT_CNT[15..8]  - (RO) TXCMDRPT without matching vector count
                                     (For debug RPT)
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_BN0REC4_BN0_AGG_VEC_TOUT_CNT_ADDR   BN1_WF_DMA_TOP_DBG_BN0REC4_ADDR
#define BN1_WF_DMA_TOP_DBG_BN0REC4_BN0_AGG_VEC_TOUT_CNT_MASK   0x0000FF00                // BN0_AGG_VEC_TOUT_CNT[15..8]
#define BN1_WF_DMA_TOP_DBG_BN0REC4_BN0_AGG_VEC_TOUT_CNT_SHFT   8
#define BN1_WF_DMA_TOP_DBG_BN0REC4_BN0_RMAC_VEC_DROP_CNT_ADDR  BN1_WF_DMA_TOP_DBG_BN0REC4_ADDR
#define BN1_WF_DMA_TOP_DBG_BN0REC4_BN0_RMAC_VEC_DROP_CNT_MASK  0x000000FF                // BN0_RMAC_VEC_DROP_CNT[7..0]
#define BN1_WF_DMA_TOP_DBG_BN0REC4_BN0_RMAC_VEC_DROP_CNT_SHFT  0

/* =====================================================================================

  ---DBG_00 (0x820f7000 + 0xD0)---

    DBGR_00[31..0]               - (RU) Debug Register 00

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_00_DBGR_00_ADDR                     BN1_WF_DMA_TOP_DBG_00_ADDR
#define BN1_WF_DMA_TOP_DBG_00_DBGR_00_MASK                     0xFFFFFFFF                // DBGR_00[31..0]
#define BN1_WF_DMA_TOP_DBG_00_DBGR_00_SHFT                     0

/* =====================================================================================

  ---DBG_01 (0x820f7000 + 0xD4)---

    DBGR_01[31..0]               - (RU) Debug Register 01

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_01_DBGR_01_ADDR                     BN1_WF_DMA_TOP_DBG_01_ADDR
#define BN1_WF_DMA_TOP_DBG_01_DBGR_01_MASK                     0xFFFFFFFF                // DBGR_01[31..0]
#define BN1_WF_DMA_TOP_DBG_01_DBGR_01_SHFT                     0

/* =====================================================================================

  ---DBG_CTRL (0x820f7000 + 0xDC)---

    RESERVED0[15..0]             - (RO) Reserved bits
    DBG_UID_SEL[22..16]          - (RW) Specify the interested UID
    RESERVED23[23]               - (RO) Reserved bits
    DBG_BYTE_SEL[26..24]         - (RW) Selects debug byte of bus signals
                                     0: bit[7:0]
                                     1: bit[15:8]
                                     2: bit[23:16]
                                     3: bit[31:24]
                                     4: bit[39:32]
                                     5: bit[47:40]
                                     6: bit[55:48]
                                     7: bit[63:56]
    RESERVED27[27]               - (RO) Reserved bits
    RPT_DBG_CNT_CLR[28]          - (RW) Clear report debug count
                                     0: Not clear
                                     1: Clear
    RESERVED29[30..29]           - (RO) Reserved bits
    ERR_IND_CLR[31]              - (RW) Clears error indicator status
                                     0: Not clear
                                     1: Clear

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_CTRL_ERR_IND_CLR_ADDR               BN1_WF_DMA_TOP_DBG_CTRL_ADDR
#define BN1_WF_DMA_TOP_DBG_CTRL_ERR_IND_CLR_MASK               0x80000000                // ERR_IND_CLR[31]
#define BN1_WF_DMA_TOP_DBG_CTRL_ERR_IND_CLR_SHFT               31
#define BN1_WF_DMA_TOP_DBG_CTRL_RPT_DBG_CNT_CLR_ADDR           BN1_WF_DMA_TOP_DBG_CTRL_ADDR
#define BN1_WF_DMA_TOP_DBG_CTRL_RPT_DBG_CNT_CLR_MASK           0x10000000                // RPT_DBG_CNT_CLR[28]
#define BN1_WF_DMA_TOP_DBG_CTRL_RPT_DBG_CNT_CLR_SHFT           28
#define BN1_WF_DMA_TOP_DBG_CTRL_DBG_BYTE_SEL_ADDR              BN1_WF_DMA_TOP_DBG_CTRL_ADDR
#define BN1_WF_DMA_TOP_DBG_CTRL_DBG_BYTE_SEL_MASK              0x07000000                // DBG_BYTE_SEL[26..24]
#define BN1_WF_DMA_TOP_DBG_CTRL_DBG_BYTE_SEL_SHFT              24
#define BN1_WF_DMA_TOP_DBG_CTRL_DBG_UID_SEL_ADDR               BN1_WF_DMA_TOP_DBG_CTRL_ADDR
#define BN1_WF_DMA_TOP_DBG_CTRL_DBG_UID_SEL_MASK               0x007F0000                // DBG_UID_SEL[22..16]
#define BN1_WF_DMA_TOP_DBG_CTRL_DBG_UID_SEL_SHFT               16

/* =====================================================================================

  ---WTMR0 (0x820f7000 + 0xE0)---

    RESERVED0[23..0]             - (RO) Reserved bits
    BN0_TXS_WT_CNT_CLR[24]       - (WO) Write 1 to clear the "TXS_WT_TIME" counter.
                                     Read always returns 0.
    BN0_CRX_WT_CNT_CLR[25]       - (WO) Write 1 to clear the "VEC_WT_TIME" counter.
                                     Read always returns 0.
    BN0_PRX_WT_CNT_CLR[26]       - (WO) Write 1 to clear the "DRFB_WT_TIME" counter.
                                     Read always returns 0.
    RESERVED27[27]               - (RO) Reserved bits
    BN0_TXS_WT_CNT_EN[28]        - (RW) Enables "TXS_WT_TIME" counter
                                     0: Disable
                                     1: Enable
    BN0_CRX_WT_CNT_EN[29]        - (RW) Enables "CRX_WT_TIME" counter
                                     0: Disable
                                     1: Enable
    BN0_PRX_WT_CNT_EN[30]        - (RW) Enable the "PRX_WT_TIME" counter
                                     0: disable
                                     1: enable
                                     (for BAND0)
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_WTMR0_BN0_PRX_WT_CNT_EN_ADDR            BN1_WF_DMA_TOP_WTMR0_ADDR
#define BN1_WF_DMA_TOP_WTMR0_BN0_PRX_WT_CNT_EN_MASK            0x40000000                // BN0_PRX_WT_CNT_EN[30]
#define BN1_WF_DMA_TOP_WTMR0_BN0_PRX_WT_CNT_EN_SHFT            30
#define BN1_WF_DMA_TOP_WTMR0_BN0_CRX_WT_CNT_EN_ADDR            BN1_WF_DMA_TOP_WTMR0_ADDR
#define BN1_WF_DMA_TOP_WTMR0_BN0_CRX_WT_CNT_EN_MASK            0x20000000                // BN0_CRX_WT_CNT_EN[29]
#define BN1_WF_DMA_TOP_WTMR0_BN0_CRX_WT_CNT_EN_SHFT            29
#define BN1_WF_DMA_TOP_WTMR0_BN0_TXS_WT_CNT_EN_ADDR            BN1_WF_DMA_TOP_WTMR0_ADDR
#define BN1_WF_DMA_TOP_WTMR0_BN0_TXS_WT_CNT_EN_MASK            0x10000000                // BN0_TXS_WT_CNT_EN[28]
#define BN1_WF_DMA_TOP_WTMR0_BN0_TXS_WT_CNT_EN_SHFT            28
#define BN1_WF_DMA_TOP_WTMR0_BN0_PRX_WT_CNT_CLR_ADDR           BN1_WF_DMA_TOP_WTMR0_ADDR
#define BN1_WF_DMA_TOP_WTMR0_BN0_PRX_WT_CNT_CLR_MASK           0x04000000                // BN0_PRX_WT_CNT_CLR[26]
#define BN1_WF_DMA_TOP_WTMR0_BN0_PRX_WT_CNT_CLR_SHFT           26
#define BN1_WF_DMA_TOP_WTMR0_BN0_CRX_WT_CNT_CLR_ADDR           BN1_WF_DMA_TOP_WTMR0_ADDR
#define BN1_WF_DMA_TOP_WTMR0_BN0_CRX_WT_CNT_CLR_MASK           0x02000000                // BN0_CRX_WT_CNT_CLR[25]
#define BN1_WF_DMA_TOP_WTMR0_BN0_CRX_WT_CNT_CLR_SHFT           25
#define BN1_WF_DMA_TOP_WTMR0_BN0_TXS_WT_CNT_CLR_ADDR           BN1_WF_DMA_TOP_WTMR0_ADDR
#define BN1_WF_DMA_TOP_WTMR0_BN0_TXS_WT_CNT_CLR_MASK           0x01000000                // BN0_TXS_WT_CNT_CLR[24]
#define BN1_WF_DMA_TOP_WTMR0_BN0_TXS_WT_CNT_CLR_SHFT           24

/* =====================================================================================

  ---WTMR1 (0x820f7000 + 0xE4)---

    BN0_TXS_WT_TIME[7..0]        - (RW) Total time of waiting TXS buffer event
                                     Unit: 1us
                                     The counter can be cleared by writing 1 to TXS_WT_CNT_CLR or writing 0 to this field.
    BN0_CRX_WT_TIME[15..8]       - (RW) Total time of waiting VEC buffer event
                                     Unit: 1us
                                     The counter can be cleared by writing 1 to VEC_WT_CNT_CLR or writing 0 to this field.
    BN0_PRX_WT_TIME[23..16]      - (RW) Total time of waiting DupRFB buffer 
                                     Unit: 1us
                                     The counter can be cleared by writing 1 to RX_WT_CNT_CLR or writing 0 to this field.
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_WTMR1_BN0_PRX_WT_TIME_ADDR              BN1_WF_DMA_TOP_WTMR1_ADDR
#define BN1_WF_DMA_TOP_WTMR1_BN0_PRX_WT_TIME_MASK              0x00FF0000                // BN0_PRX_WT_TIME[23..16]
#define BN1_WF_DMA_TOP_WTMR1_BN0_PRX_WT_TIME_SHFT              16
#define BN1_WF_DMA_TOP_WTMR1_BN0_CRX_WT_TIME_ADDR              BN1_WF_DMA_TOP_WTMR1_ADDR
#define BN1_WF_DMA_TOP_WTMR1_BN0_CRX_WT_TIME_MASK              0x0000FF00                // BN0_CRX_WT_TIME[15..8]
#define BN1_WF_DMA_TOP_WTMR1_BN0_CRX_WT_TIME_SHFT              8
#define BN1_WF_DMA_TOP_WTMR1_BN0_TXS_WT_TIME_ADDR              BN1_WF_DMA_TOP_WTMR1_ADDR
#define BN1_WF_DMA_TOP_WTMR1_BN0_TXS_WT_TIME_MASK              0x000000FF                // BN0_TXS_WT_TIME[7..0]
#define BN1_WF_DMA_TOP_WTMR1_BN0_TXS_WT_TIME_SHFT              0

/* =====================================================================================

  ---SPCR0 (0x820f7000 + 0xEC)---

    SPCR_DF1[15..0]              - (RW) Default 1 control registers
    SPCR_DF0[31..16]             - (RW) Default 0 control registers

 =====================================================================================*/
#define BN1_WF_DMA_TOP_SPCR0_SPCR_DF0_ADDR                     BN1_WF_DMA_TOP_SPCR0_ADDR
#define BN1_WF_DMA_TOP_SPCR0_SPCR_DF0_MASK                     0xFFFF0000                // SPCR_DF0[31..16]
#define BN1_WF_DMA_TOP_SPCR0_SPCR_DF0_SHFT                     16
#define BN1_WF_DMA_TOP_SPCR0_SPCR_DF1_ADDR                     BN1_WF_DMA_TOP_SPCR0_ADDR
#define BN1_WF_DMA_TOP_SPCR0_SPCR_DF1_MASK                     0x0000FFFF                // SPCR_DF1[15..0]
#define BN1_WF_DMA_TOP_SPCR0_SPCR_DF1_SHFT                     0

/* =====================================================================================

  ---BN0ICSCFR0 (0x820f7000 + 0xF0)---

    BN0_ICS_QID[6..0]            - (RW) ICS destination queue index
                                     2'h0: Qeue index is 0
                                     2'h1: Queue index is 1
                                     2'h2: Queue index is 2
                                     2'h3: Queue index is 3
                                     2'h4: Queue index is 4
                                     2'h5: Queue index is 5
                                     (Both TX/RX)
    RESERVED7[7]                 - (RO) Reserved bits
    BN0_ICS_PID[9..8]            - (RW) ICS destination port index
                                     2'h0: HIF or WM-CPU (MAC_DMA0 or MAC_DMA1)
                                     2'h1: MCU
                                     (Both TX/RX)
    RESERVED10[15..10]           - (RO) Reserved bits
    BN0_ICS_TOUT[23..16]         - (RW) ICS timeout value
                                     Unit: 32us
                                     Both TX/RX)
    BN0_ICS_EN[24]               - (RW) ICS report engine enable
                                     1'b0: disable
                                     1'b1: enable
                                     For TX ICS report, also need to check TMAC CR (ICSCR0) enable
                                     For RX ICS report, also need to check RMAC CR (ICSRPT) enable
    BN0_ICS_RXBF_EN[25]          - (RW) ICS RPT use PSE RX or VEC page count for Buffer Allocation
                                     1'h0: use VEC page count
                                     1'h1: use RXRPT page count
                                     (For RXRPT)
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_RXBF_EN_ADDR         BN1_WF_DMA_TOP_BN0ICSCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_RXBF_EN_MASK         0x02000000                // BN0_ICS_RXBF_EN[25]
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_RXBF_EN_SHFT         25
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_EN_ADDR              BN1_WF_DMA_TOP_BN0ICSCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_EN_MASK              0x01000000                // BN0_ICS_EN[24]
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_EN_SHFT              24
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_TOUT_ADDR            BN1_WF_DMA_TOP_BN0ICSCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_TOUT_MASK            0x00FF0000                // BN0_ICS_TOUT[23..16]
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_TOUT_SHFT            16
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_PID_ADDR             BN1_WF_DMA_TOP_BN0ICSCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_PID_MASK             0x00000300                // BN0_ICS_PID[9..8]
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_PID_SHFT             8
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_QID_ADDR             BN1_WF_DMA_TOP_BN0ICSCFR0_ADDR
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_QID_MASK             0x0000007F                // BN0_ICS_QID[6..0]
#define BN1_WF_DMA_TOP_BN0ICSCFR0_BN0_ICS_QID_SHFT             0

/* =====================================================================================

  ---BN0ICSCFR1 (0x820f7000 + 0xF4)---

    BN0_ICS_MAX_FRAME_SIZE[10..0] - (RW) To indicate if remaining agg size < max frame size, HW en-queue this report immediately (unit: Bytes)
                                     Range from 0 ~2047 bytes, default is the max ICS frame size
                                     (HW only DDW align)
    RESERVED11[15..11]           - (RO) Reserved bits
    BN0_ICS_AGG_SIZE[26..16]     - (RW) ICS maximum aggregation size (unit: Bytes)
                                     Range from 0 ~ 2047 bytes
                                     (HW only DDW align)
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_DMA_TOP_BN0ICSCFR1_BN0_ICS_AGG_SIZE_ADDR        BN1_WF_DMA_TOP_BN0ICSCFR1_ADDR
#define BN1_WF_DMA_TOP_BN0ICSCFR1_BN0_ICS_AGG_SIZE_MASK        0x07FF0000                // BN0_ICS_AGG_SIZE[26..16]
#define BN1_WF_DMA_TOP_BN0ICSCFR1_BN0_ICS_AGG_SIZE_SHFT        16
#define BN1_WF_DMA_TOP_BN0ICSCFR1_BN0_ICS_MAX_FRAME_SIZE_ADDR  BN1_WF_DMA_TOP_BN0ICSCFR1_ADDR
#define BN1_WF_DMA_TOP_BN0ICSCFR1_BN0_ICS_MAX_FRAME_SIZE_MASK  0x000007FF                // BN0_ICS_MAX_FRAME_SIZE[10..0]
#define BN1_WF_DMA_TOP_BN0ICSCFR1_BN0_ICS_MAX_FRAME_SIZE_SHFT  0

/* =====================================================================================

  ---DBG_RXS_01 (0x820f7000 + 0x100)---

    UX_DBGR_RXS_01[31..0]        - (RU) RXS debug register
                                     Note: select RX path by setting DBG_CTRL.DBG_UID_SEL

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_RXS_01_UX_DBGR_RXS_01_ADDR          BN1_WF_DMA_TOP_DBG_RXS_01_ADDR
#define BN1_WF_DMA_TOP_DBG_RXS_01_UX_DBGR_RXS_01_MASK          0xFFFFFFFF                // UX_DBGR_RXS_01[31..0]
#define BN1_WF_DMA_TOP_DBG_RXS_01_UX_DBGR_RXS_01_SHFT          0

/* =====================================================================================

  ---DBG_RXS_02 (0x820f7000 + 0x104)---

    UX_DBGR_RXS_02[31..0]        - (RU) RXS debug register
                                     Note: select RX path by setting DBG_CTRL.DBG_UID_SEL

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_RXS_02_UX_DBGR_RXS_02_ADDR          BN1_WF_DMA_TOP_DBG_RXS_02_ADDR
#define BN1_WF_DMA_TOP_DBG_RXS_02_UX_DBGR_RXS_02_MASK          0xFFFFFFFF                // UX_DBGR_RXS_02[31..0]
#define BN1_WF_DMA_TOP_DBG_RXS_02_UX_DBGR_RXS_02_SHFT          0

/* =====================================================================================

  ---DBG_RXS_03 (0x820f7000 + 0x108)---

    UX_DBGR_RXS_03[31..0]        - (RU) RXS debug register
                                     Note: select RX path by setting DBG_CTRL.DBG_UID_SEL

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_RXS_03_UX_DBGR_RXS_03_ADDR          BN1_WF_DMA_TOP_DBG_RXS_03_ADDR
#define BN1_WF_DMA_TOP_DBG_RXS_03_UX_DBGR_RXS_03_MASK          0xFFFFFFFF                // UX_DBGR_RXS_03[31..0]
#define BN1_WF_DMA_TOP_DBG_RXS_03_UX_DBGR_RXS_03_SHFT          0

/* =====================================================================================

  ---DBG_RXS_04 (0x820f7000 + 0x10C)---

    UX_DBGR_RXS_04[31..0]        - (RU) RXS debug register
                                     Note: select RX path by setting DBG_CTRL.DBG_UID_SEL

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_RXS_04_UX_DBGR_RXS_04_ADDR          BN1_WF_DMA_TOP_DBG_RXS_04_ADDR
#define BN1_WF_DMA_TOP_DBG_RXS_04_UX_DBGR_RXS_04_MASK          0xFFFFFFFF                // UX_DBGR_RXS_04[31..0]
#define BN1_WF_DMA_TOP_DBG_RXS_04_UX_DBGR_RXS_04_SHFT          0

/* =====================================================================================

  ---DBG_RXS_05 (0x820f7000 + 0x110)---

    UX_DBGR_RXS_05[31..0]        - (RU) RXS debug register
                                     Note: select RX path by setting DBG_CTRL.DBG_UID_SEL

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_RXS_05_UX_DBGR_RXS_05_ADDR          BN1_WF_DMA_TOP_DBG_RXS_05_ADDR
#define BN1_WF_DMA_TOP_DBG_RXS_05_UX_DBGR_RXS_05_MASK          0xFFFFFFFF                // UX_DBGR_RXS_05[31..0]
#define BN1_WF_DMA_TOP_DBG_RXS_05_UX_DBGR_RXS_05_SHFT          0

/* =====================================================================================

  ---DBG_RXS_06 (0x820f7000 + 0x114)---

    UX_DBGR_RXS_06[31..0]        - (RU) RXS debug register
                                     Note: select RX path by setting DBG_CTRL.DBG_UID_SEL

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_RXS_06_UX_DBGR_RXS_06_ADDR          BN1_WF_DMA_TOP_DBG_RXS_06_ADDR
#define BN1_WF_DMA_TOP_DBG_RXS_06_UX_DBGR_RXS_06_MASK          0xFFFFFFFF                // UX_DBGR_RXS_06[31..0]
#define BN1_WF_DMA_TOP_DBG_RXS_06_UX_DBGR_RXS_06_SHFT          0

/* =====================================================================================

  ---DBG_FID_01 (0x820f7000 + 0x140)---

    BNX_CRX_RPT_FID[11..0]       - (RU) the destination FID of CRX RPT packet
                                     Note: select Band by setting DBG_CTRL.DBG_BNX_SEL
    RESERVED12[14..12]           - (RO) Reserved bits
    BNX_CRX_RPT_FID_RDY[15]      - (RU) Indicates the destination FID of CRX RPT packet is owned by LMAC
                                     Note: select Band by setting DBG_CTRL.DBG_BNX_SEL
    BNX_CRX_VEC_FID[27..16]      - (RU) the destination FID of CRX VEC packet
                                     Note: select Band by setting DBG_CTRL.DBG_BNX_SEL
    RESERVED28[30..28]           - (RO) Reserved bits
    BNX_CRX_VEC_FID_RDY[31]      - (RU) Indicates the destination FID of CRX VEC packet is owned by LMAC
                                     Note: select Band by setting DBG_CTRL.DBG_BNX_SEL

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_FID_01_BNX_CRX_VEC_FID_RDY_ADDR     BN1_WF_DMA_TOP_DBG_FID_01_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_01_BNX_CRX_VEC_FID_RDY_MASK     0x80000000                // BNX_CRX_VEC_FID_RDY[31]
#define BN1_WF_DMA_TOP_DBG_FID_01_BNX_CRX_VEC_FID_RDY_SHFT     31
#define BN1_WF_DMA_TOP_DBG_FID_01_BNX_CRX_VEC_FID_ADDR         BN1_WF_DMA_TOP_DBG_FID_01_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_01_BNX_CRX_VEC_FID_MASK         0x0FFF0000                // BNX_CRX_VEC_FID[27..16]
#define BN1_WF_DMA_TOP_DBG_FID_01_BNX_CRX_VEC_FID_SHFT         16
#define BN1_WF_DMA_TOP_DBG_FID_01_BNX_CRX_RPT_FID_RDY_ADDR     BN1_WF_DMA_TOP_DBG_FID_01_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_01_BNX_CRX_RPT_FID_RDY_MASK     0x00008000                // BNX_CRX_RPT_FID_RDY[15]
#define BN1_WF_DMA_TOP_DBG_FID_01_BNX_CRX_RPT_FID_RDY_SHFT     15
#define BN1_WF_DMA_TOP_DBG_FID_01_BNX_CRX_RPT_FID_ADDR         BN1_WF_DMA_TOP_DBG_FID_01_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_01_BNX_CRX_RPT_FID_MASK         0x00000FFF                // BNX_CRX_RPT_FID[11..0]
#define BN1_WF_DMA_TOP_DBG_FID_01_BNX_CRX_RPT_FID_SHFT         0

/* =====================================================================================

  ---DBG_FID_02 (0x820f7000 + 0x144)---

    UX_PRX_FID[11..0]            - (RU) the destination FID of PRX packet
                                     Note: select RX path by setting DBG_CTRL.DBG_UID_SEL
    RESERVED12[14..12]           - (RO) Reserved bits
    UX_PRX_FID_RDY[15]           - (RU) Indicates the destination FID of PRX packet is owned by LMAC
                                     Note: select PRX path by setting DBG_CTRL.DBG_UID_SEL
    BNX_RE_RPT_FID[27..16]       - (RU) the destination FID of CMDRPT or RXRPT packet
    RESERVED28[30..28]           - (RO) Reserved bits
    BNX_RE_RPT_FID_RDY[31]       - (RU) Indicates the destination FID of CMDRPT or RXRPT packet is owned by LMAC

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_FID_02_BNX_RE_RPT_FID_RDY_ADDR      BN1_WF_DMA_TOP_DBG_FID_02_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_02_BNX_RE_RPT_FID_RDY_MASK      0x80000000                // BNX_RE_RPT_FID_RDY[31]
#define BN1_WF_DMA_TOP_DBG_FID_02_BNX_RE_RPT_FID_RDY_SHFT      31
#define BN1_WF_DMA_TOP_DBG_FID_02_BNX_RE_RPT_FID_ADDR          BN1_WF_DMA_TOP_DBG_FID_02_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_02_BNX_RE_RPT_FID_MASK          0x0FFF0000                // BNX_RE_RPT_FID[27..16]
#define BN1_WF_DMA_TOP_DBG_FID_02_BNX_RE_RPT_FID_SHFT          16
#define BN1_WF_DMA_TOP_DBG_FID_02_UX_PRX_FID_RDY_ADDR          BN1_WF_DMA_TOP_DBG_FID_02_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_02_UX_PRX_FID_RDY_MASK          0x00008000                // UX_PRX_FID_RDY[15]
#define BN1_WF_DMA_TOP_DBG_FID_02_UX_PRX_FID_RDY_SHFT          15
#define BN1_WF_DMA_TOP_DBG_FID_02_UX_PRX_FID_ADDR              BN1_WF_DMA_TOP_DBG_FID_02_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_02_UX_PRX_FID_MASK              0x00000FFF                // UX_PRX_FID[11..0]
#define BN1_WF_DMA_TOP_DBG_FID_02_UX_PRX_FID_SHFT              0

/* =====================================================================================

  ---DBG_FID_03 (0x820f7000 + 0x148)---

    BNX_TXS2H_FID[11..0]         - (RU) the destination FID of TXS2H packet
                                     Note: select Band by setting DBG_CTRL.DBG_BNX_SEL
    RESERVED12[14..12]           - (RO) Reserved bits
    BNX_TXS2H_FID_RDY[15]        - (RU) Indicates the destination FID of TXS2H packet is owned by LMAC
                                     Note: select Band by setting DBG_CTRL.DBG_BNX_SEL
    BNX_TXS2M_FID[27..16]        - (RU) the destination FID of TXS2M packet
                                     Note: select Band by setting DBG_CTRL.DBG_BNX_SEL
    RESERVED28[30..28]           - (RO) Reserved bits
    BNX_TXS2M_FID_RDY[31]        - (RU) Indicates the destination FID of TXS2M packet is owned by LMAC
                                     Note: select Band by setting DBG_CTRL.DBG_BNX_SEL

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_FID_03_BNX_TXS2M_FID_RDY_ADDR       BN1_WF_DMA_TOP_DBG_FID_03_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_03_BNX_TXS2M_FID_RDY_MASK       0x80000000                // BNX_TXS2M_FID_RDY[31]
#define BN1_WF_DMA_TOP_DBG_FID_03_BNX_TXS2M_FID_RDY_SHFT       31
#define BN1_WF_DMA_TOP_DBG_FID_03_BNX_TXS2M_FID_ADDR           BN1_WF_DMA_TOP_DBG_FID_03_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_03_BNX_TXS2M_FID_MASK           0x0FFF0000                // BNX_TXS2M_FID[27..16]
#define BN1_WF_DMA_TOP_DBG_FID_03_BNX_TXS2M_FID_SHFT           16
#define BN1_WF_DMA_TOP_DBG_FID_03_BNX_TXS2H_FID_RDY_ADDR       BN1_WF_DMA_TOP_DBG_FID_03_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_03_BNX_TXS2H_FID_RDY_MASK       0x00008000                // BNX_TXS2H_FID_RDY[15]
#define BN1_WF_DMA_TOP_DBG_FID_03_BNX_TXS2H_FID_RDY_SHFT       15
#define BN1_WF_DMA_TOP_DBG_FID_03_BNX_TXS2H_FID_ADDR           BN1_WF_DMA_TOP_DBG_FID_03_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_03_BNX_TXS2H_FID_MASK           0x00000FFF                // BNX_TXS2H_FID[11..0]
#define BN1_WF_DMA_TOP_DBG_FID_03_BNX_TXS2H_FID_SHFT           0

/* =====================================================================================

  ---DBG_FID_04 (0x820f7000 + 0x14C)---

    UX_TX_PSE_FID[11..0]         - (RU) the source FID of TX packet
                                     Note : select TX path by setting DBG_CTRL.DBG_UID_SEL
    RESERVED12[14..12]           - (RO) Reserved bits
    UX_TX_PSE_FID_RDY[15]        - (RU) Indicates the source FID of TX packet is latched by LMAC
                                     Note: select TX path by setting DBG_CTRL.DBG_UID_SEL
    UX_TX_PLE_FID[27..16]        - (RU) the source FID of TXD
                                     Note: select TX path by setting DBG_CTRL.DBG_UID_SEL
    RESERVED28[30..28]           - (RO) Reserved bits
    UX_TX_PLE_FID_RDY[31]        - (RU) Indicates the source FID of TXD is latched by LMAC
                                     Note: select TX path by setting DBG_CTRL.DBG_UID_SEL

 =====================================================================================*/
#define BN1_WF_DMA_TOP_DBG_FID_04_UX_TX_PLE_FID_RDY_ADDR       BN1_WF_DMA_TOP_DBG_FID_04_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_04_UX_TX_PLE_FID_RDY_MASK       0x80000000                // UX_TX_PLE_FID_RDY[31]
#define BN1_WF_DMA_TOP_DBG_FID_04_UX_TX_PLE_FID_RDY_SHFT       31
#define BN1_WF_DMA_TOP_DBG_FID_04_UX_TX_PLE_FID_ADDR           BN1_WF_DMA_TOP_DBG_FID_04_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_04_UX_TX_PLE_FID_MASK           0x0FFF0000                // UX_TX_PLE_FID[27..16]
#define BN1_WF_DMA_TOP_DBG_FID_04_UX_TX_PLE_FID_SHFT           16
#define BN1_WF_DMA_TOP_DBG_FID_04_UX_TX_PSE_FID_RDY_ADDR       BN1_WF_DMA_TOP_DBG_FID_04_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_04_UX_TX_PSE_FID_RDY_MASK       0x00008000                // UX_TX_PSE_FID_RDY[15]
#define BN1_WF_DMA_TOP_DBG_FID_04_UX_TX_PSE_FID_RDY_SHFT       15
#define BN1_WF_DMA_TOP_DBG_FID_04_UX_TX_PSE_FID_ADDR           BN1_WF_DMA_TOP_DBG_FID_04_ADDR
#define BN1_WF_DMA_TOP_DBG_FID_04_UX_TX_PSE_FID_MASK           0x00000FFF                // UX_TX_PSE_FID[11..0]
#define BN1_WF_DMA_TOP_DBG_FID_04_UX_TX_PSE_FID_SHFT           0

#ifdef __cplusplus
}
#endif

#endif // __BN1_WF_DMA_TOP_REGS_H__
